The Very Large Scale Integration (VLSI) Design Course is designed to bridge the gap between academic knowledge and industry requirements in semiconductor design. With the increasing demand for skilled chip designers in the global market, this program provides hands-on training in front-end RTL design, verification, and back-end physical design, along with exposure to EDA tools from Cadence, Synopsys, and Siemens/Mentor Graphics.
By the end of the program, participants will gain the expertise required to work on real-world chip design projects, making them job-ready for the semiconductor industry.
Students: B.Tech/M.Tech in ECE, EEE, CSE, IT
Fresh Graduates: Looking to build careers in semiconductor/VLSI
Working Professionals: Transitioning into VLSI or upgrading skills
Researchers: Interested in chip design and advanced EDA flows
Industry-standard VLSI design flow: RTL → GDSII
Hands-on projects with real EDA tools (Cadence, Synopsys, Siemens)
Focus on both Front-end (RTL, Verification, DFT, Low Power) and Back-end (Synthesis, APR, STA, Signoff)
Exposure to latest technology nodes (28nm, 18nm, etc.)
Live mentoring from experienced semiconductor professionals
Resume building, interview preparation, and placement assistance
By completing this course, you will be able to:
Understand the entire VLSI design flow from specification to fabrication.
Design and implement RTL in Verilog/SystemVerilog.
Apply functional verification using advanced methodologies (UVM).
Perform synthesis, timing closure, floorplanning, placement & routing.
Understand Design for Testability (DFT), Low Power Design, CDC, LEC, SDC concepts.
Gain confidence in handling EDA tools used in industry projects.