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Design For Testability (PPTs & Assignments)

Created by

Ravi Desaboina

Hours

9 Enrolled

(0 Reviews)

English

Last updated

Thu, 10-Sep-2026

Course description

What will i learn?

Requirements

1.1 Foundation of DFT in VLSI
1.2 Basics of Digital Design
1.3 Introduction to DFT & SOC Test flow

2.1 Introduction to Scan Insertion
2.2 Scan Chain operation
2.3 scan methodology
2.4 Scan insertion by tool

Scan Compression

4.1 ATPG Introduction
4.2 ATPG Fault models
4.3 Fault classes part-1
4.4 Fault classes part-2

On chip clock controller

6.1 JTAG
6.2 Input and output wrapper cell

IJTAG Architecture

8.1 Memory & MBIST part-1
8.2 MBIST test Algorithms

Genus tool Script part 1
Genus tool script part 2

Ravi Desaboina

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Manvadithya Pinisetty

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₹90000

Lectures

20

Skill level

Beginner

Expiry period

Lifetime

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Design For Testability (PPTs & Assignments)

Course description

What will i learn?

Requirements

Module-1 Foundation 3 Lessons Hours

Module -2 Scan insertion 4 Lessons Hours

Module-3 Compression 1 Lessons Hours

module-4 ATPG 4 Lessons Hours

Module 5 CLock 1 Lessons Hours

Module 6 JTAG & wrapper cells 2 Lessons Hours

Module 7 IJTAG 1 Lessons Hours

Module 8 - MBIST 2 Lessons Hours

Assignments 0 Lessons Hours

Genus Tool Script 2 Lessons Hours

Ravi Desaboina

Manvadithya Pinisetty

₹90000

Lectures

20

Skill level

Beginner

Expiry period

Lifetime

Related courses

Top categories

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